The present invention generally relates to a digital controller of the type used for process controls or the like. More particularly, the invention concerns a digital controller which can be advantageously used for process control in which a plurality of processes are to be controlled by performing arithmetic processings of a like type or nature.
The control of plural objectives by means of a digital controller has the disadvantage that the overall processing speed becomes slow in proportion to the number of the objectives to be controlled, when the control is performed serially on a time division basis. With the present invention, it is intended to provide a digital controller which is capable of controlling a number of objectives with high speed through parallel arithmetic processings.
For performing high speed arithmetic processings, it has been known to use a parallel arithmetic processing procedure. Among others, the procedure disclosed in U.S. Pat. No. 3,364,472 may be mentioned, which concerns a parallel network type computer system. In addition to the network system, other parallel arithmetic processing systems are known.
Further, a technique for performing parallel logic operations and equipment for performing data logic analysis by computer hardware processing are disclosed in G.B. Pat. No. 1,456,941. This patent concerns a parallel processing system for data processing in which a plurality of functional units process data in an overlapping manner in accordance with a predetermined instruction sequence.
In recent years, as the various processes and systems become more sophisticated in scale and performance, there arises a demand for a programmable controller having high speed and high reliability for controlling such processes and systems. Heretofore, efforts for realizing a high speed operation have been made primarily in connection with the hardware structure of a microcomputer. However, a limitation will be imposed on further development of the hardware which permits higher operation speed, not to speak of the manufacturing cost. As a system which is designed to assure a high speed operation and high reliability, there may be mentioned a multi-processor system. However, the conventional multi-processor system is so arranged that the individual processors perform independent processings in parallel. As a consequence, the waiting time in reading a program through a common bus presents a problem. Besides, time loss due to the overhead of a control program for supervisory control of the multi-processor system gives rise to another problem, providing an obstacle to realization of the expected high speed operation. In case the processings have to be performed by controlling the timing among the processors, the waiting time involved among the processors as well as the complicated program for maintaining synchronism among operations of the processors provides disadvantages. In case the outputs of the individual processors of the multi-processor system have to be compared with one another for assuring an increased reliability, it is necessary to provide the erroneous operation detecting period with a margin for disposing of any timing difference among the processors, thereby involving further complexity and rendering it impossible to accomplish detection with high precision, with results in other disadvantages.